DESIGN OF DIGITAL CIRCUITS USING REVERSIBLE LOGIC AT 32nm TECHNOLOGY

1 M.Tech student, Dept. of ECE, VLSI System Design, JNTUA, Ananthapuramu, Andhra Pradesh, India. 2Member of Technical Staff, SEER Academy, Hyderabad, India. ---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Reversible logic has presented itself as a prominent technology which plays an imperative role in Quantum Computing. Quantum computing devices theoretically operate at ultra high speed and consume less power. Research done in this paper aims to utilize the idea of reversible logic to break the conventional speed-power trade-off, there by getting a step closer to realize Quantum computing devices. To authenticate this research, various Digital circuits are implemented such as a 4-bit Ripple-carry Adder, 8-bit Wallace Tree Multiplier, and 16bit GCD unit are implemented using Reversible Logic. The power and area parameters for the circuits have been indicated, and compared with the 32nm and 90 nm Technologies. The comparative statistical study proves that circuits employing 32nm technology Reversible Digital Circuits are area and power efficient. The designs presented in this paper were simulated using VCS-Synopsys.